This invention relates to a method of fabricating a semiconductor device.
D. D. Tang, P. M. Solomon, T. H. Ning, R. D. Isaac and R. E. Burger, "1.25 .mu.m Deep-Groove-Isolated Self-Aligned Bipolar Circuits," IEEE J. Solid-State Circuits, vol. SC-17, 925 (1982), discloses a method of fabricating an n-p-n transistor in which a first photomasking operation is used to define an area that is to receive a p-type implant, and will eventually contain the base of the transistor, and a second photomasking operation is used to pattern a layer of polysilicon, which forms a base contact and from which p-type dopant is diffused into the area that received the p-type implant, to form an extrinsic base. Therefore, this fabrication method is subject to the disadvantage that the area that receives the initial p-type implant must be sufficiently large to accommodate possible misalignment of the mask that is used to define the polysilicon base contact.
S. Konaka, Y. Yamamoto and T. Sakai, "A 30-ps Si Bipolar IC Using Super Self-Aligned Process Technology," IEEE Trans. Electron Devices, vol. ED-33, 526 (1986), describes a method of fabricating an n- p n transistor in which the emitter is self-aligned with respect to the base contact and the base contact is self-aligned with respect to the base, and therefore only one photomasking operation is required in order to form the transistor. In this method, a silicon nitride layer is formed over the region of the substrate in which the transistor is to be formed, and a layer of polysilicon is deposited over the silicon nitride layer. The polysilicon over the area corresponding to the emitter and base of the transistor is removed by a photomasking and etching operation, exposing the silicon nitride layer, and a surface layer of the polysilicon that remains is oxidized. The silicon nitride exposed by removal of polysilicon is removed by etching, and during the etching silicon nitride is removed from under the polysilicon, leaving a cavity. Polysilicon is deposited into the cavity providing a connection between the first deposit of polysilicon and the region that will be the base of the transistor. This method is subject to the disadvantage that it is difficult to control the side etching operation whereby the silicon nitride underneath the polysilicon is removed. Moreover, it is possible that voids will be formed when the polysilicon is deposited into the cavity formed by the side etching operation, so that reliability of connections between the first deposit of polysilicon and the base can be ensured.
T. Sakai et al, "Prospects of SST Technology for High Speed LSI", 1985 IEDM Tech. Dig., 18-21, describes a method that is similar to that described in S. Konaka et al.